1. Field of the Invention
The present invention relates to a power supply circuit provided with a booster circuit that boosts the power supply voltage.
2. Background of the Invention
There already exists a power supply circuit that boosts the power supply voltage before supplying the voltage to a non-volatile semiconductor memory device, such as a NAND-type EEPROM.
Such a conventional power supply circuit has a booster circuit that boosts the voltage supplied from a power supply to produce an output voltage, a resistor circuit for monitoring the output voltage, and a comparator/detector circuit that outputs a signal indicating whether to activate or deactivate the booster circuit based on the value of the monitored voltage provided by the resistor circuit (see Japanese Patent Laid-Open No. 2003-199329, for example).
If the output voltage decreases because of a load connected to the power supply circuit, the comparator/detector circuit detects the decrease in voltage and outputs a signal to activate the booster circuit, and the booster circuit boosts the voltage. In this way, the power supply voltage can restore the voltage to a desired value.
However, there is a certain time lag between the time when the load is connected to the power supply circuit and the time when the comparator/detector circuit detects the decrease in voltage and outputs the signal to activate the booster circuit. The time lag is determined by the activation time constant, which is determined by the resistance of the resistor circuit, and the response time of the comparator/detector circuit.
To reduce the current consumption, the resistor circuit of the conventional power supply circuit has a resistor having an extremely high resistance, thereby minimizing the value of the current flowing through the resistor circuit. Therefore, there is a problem that the time constant, which is determined by the resistance, is large, and it takes a quite long time to restore the output voltage to a set potential.
To shorten the time to restore the output voltage, the resistance of the resistor circuit can be reduced to reduce the activation time constant of the voltage detector circuit, thereby shortening the response time. However, in this case, the leak current from the output of the booster circuit increases.
Alternatively, the capacity for boosting can be increased to enhance the capability of the booster circuit, thereby shortening the time to restore the output voltage. However, the size of the booster circuit increases, and the area for the booster circuit will also be increased.